(1) Field of the Invention
The present invention relates to integrated circuits built on semiconductor substrates, and more particularly to a method for fabricating dynamic random access memory (DRAM) using a novel stacked capacitor process for increased capacitance and increased memory cell density.
(2) Description of the Prior Art
The circuit density on integrated circuits has continually increased over the years due to innovations in process technologies. One particular device with increased density is the dynamic random access memory (DRAM), which is expected to have more than a billion memory cells (gigabits) by the year 2000 or shortly thereafter. This higher density of memory cells is a result of improved high resolution photolithography and patterning by directional (anisotropic) plasma etching, which result in reduced device sizes. However, this reduction in device size is putting additional demand on the semiconductor processing technologies, and also on maintaining the electrical requirements, such as maintaining or increasing the capacitance of capacitors on DRAM devices.
These DRAM devices consist in part of an array of individual DRAM storage cells that store binary data (bits) as electrical charge on a storage capacitor. Further, the information is stored and retrieved from the storage capacitor by means of a single pass transistor in each memory cell, and by address and read/write circuits on the periphery of the DRAM chip. The pass transistor is usually a field effect transistor (FET), and the single capacitor in each cell is either formed in the semiconductor substrate as a trench capacitor, or built over the FET in the cell area as a stacked capacitor. To maintain a reasonable DRAM chip size and improved circuit performance, it is necessary to further reduce the area occupied by the individual cells on the DRAM chip. Unfortunately, as the cell size decreases, it becomes increasing more difficult to fabricate stacked or trench storage capacitors with sufficient capacitance to store the necessary charge to provide an acceptable signal-to-noise level for the read circuits (sense amplifiers) to detect. The reduced charge also requires increased refresh cycles that periodically restore the charge on these volatile storage cells. This further reduces the performance of the DRAM circuit.
Since the capacitor area is limited to the cell size in order to accommodate the multitude of cells on the DRAM chip, it is necessary to explore alternative methods for increasing the capacitance without increasing the lateral area that the capacitor occupies on the substrate surface. In recent years the method of choice is to build stacked capacitors over the pass transistors within each cell area, rather than forming trench capacitors which need to be etched to increasing depths in the substrate to maintain the necessary capacitance. The stacked capacitors provide increased latitude in capacitor design and processing while reducing cell area. More specifically, the stacked capacitors can be built in the vertical extensions (third dimension) to increase the stacked capacitor area, and therefore to increase the capacitance.
Numerous methods have been reported in the literature for making stacked storage capacitors with vertical structures to increase capacitance and packing density of the DRAM cells. In U.S. Pat. No. 5,399,518 Sim et al. teach a method for making a multiple walled capacitor using sidewall spacers as a mask to pattern the bottom electrode for the capacitor. Another approach is taught by Roh in U.S. Pat. No. 5,545,582 in which a first material layer is deposited on a node first conductive layer and patterned. Then a series of depositions and anisotropic etchbacks are used to form vertical sidewalls for the bottom electrode (node electrode) resulting in a double-walled capacitor. Another approach is taught by Tseng, U.S. Pat. No. 5,604,146, in which an E-shaped storage capacitor is formed having a vertical wall self-aligned to a center plug (post).
However, to be cost competitive in making DRAMs, it is very desirable to further increase the capacitance while simplifying the manufacturing process.